Alexey A. Paznikov

Alexey A. Paznikov

Candidate of Science/PhD: SibSUTIS, 2013

Level of English language proficiency: Fluent

The direction of training for which the graduate student will be accepted: 09.06.01 – Computer Systems Engineering and Informatics

List of research projects of a potential supervisor (participation/guidance)

  • Adaptive compiler optimization for cache-memory usage optimization. 2021-2023. Principal Investigator..
  • Design of methods, algorithms and software for scalable synchronization for multiprocessor computer systems. 2019-2021. Principal Investigator.
  • Algorithms and software for optimizing parallel program execution in remote memory access model. 2022-2023. Principal Investigator.

    • List of possible research topics

    1. Performance engineering, compiler optimization:

      1.1.Algorithms for data layout optimization

      1.2.Algorithms for code layout optimization

      1.3.Optimizing vectorization (SIMD-instructions)

      1.4.Using profile-guided optimization for microarchitectural optimization

      1.5.Algorithms for binary code optimization

      1.6.Improving link-time optimization analysis and code transformation

    2. Shared-memory computer systems (multicore, multiprocessor):

      2.1.Scalable locks for multithreading synchronization

      2.2.Non-blocking (lock-free, wait-free) concurrent data structures

      2.3.Scalable relaxed concurrent data structures

      2.4.Scalable non-blocking atomic snapshots

      2.5.Synchronization methods for non-volatile memory (persistent synchronization)

    3. Distributed-memory computers (high-performance computing, HPC, clusters, supercomputers)

      3.1.Topology-aware algorithms of collective communications

      3.2.Optimization of thread synchronization in hybrid MPI+threads programs

      3.3.Non-blocking distributed data structures in RMA MPI model

      3.4.Non-blocking atomic snapshots for distributed-memory systems

      3.5.Lock-based synchronization in high-performance computers

    4. Applied parallel programming

      4.1.Designing efficient parallel algorithms for machine learning and reinforcement learning

      4.2.Microarchitectural optimization of machine learning algorithms

    Supervisor’s research interests

    1. Performance engineering, compiler optimization

      Microarchitectural optimization, compiler optimization, data layout optimization, code layout optimization, optimization of branches, code vectorization, cache-memory access optimization, LLVM/Clang, profile-guided optimization, interprocedural optimization (IPO), cross-module optimization (CMO, link-time optimization, LTO), binary-level optimization (post-linkage optimization).

    2. Shared-memory computer systems (multicore, multiprocessor)

      Scalable synchronization in multithreading: locks, non-blocking (lock-free, wait-free) concurrent data structures, relaxed concurrent data structures, atomic snapshots, non-volatile memory, transactional memory.

    3. Distributed-memory computers (high-performance computing, HPC, clusters, supercomputers)

      Optimizing MPI-programs, designing algorithms for message-passing: algorithms of collective communications, one-sided communications (MPI RMA model), hybrid parallel programming (MPI+threads). Distributed shared data structures for high-performance computing and synchronization algorithms. Analytical communication models.

    4. Applied parallel programming

      Designing parallel algorithms for artificial intelligence (machine learning, reinforcement learning)

    Research highlights

    1. Working on the bleeding edge of the research.
    2. Participating in real projects (in research as well as in applied and commercial fields).
    3. Finance support of post-graduate students.
    4. Cooperation with other Russian and foreign institutions and commercial companies.
    5. Use of cluster computers and supercomputers in the development process.
    6. Involvement of post-graduate students in the teaching process (if desired)

    Supervisor’s specific requirements

    • Interest (required)
    • Good motivation (required)
    • Desire to grow as a specialist (required)
    • Programming skills in C/C ++ (highly desirable)
    • Any skills in system programming, parallel programming (will be a big advantage)

    Supervisor’s main publications

    12 publications in total. 5 most significant:

    1. Paznikov A.A. Distributed relaxed queue in remote memory access model // Tomsk State University Journal of Control and Computer Science, 2020. – N 50. – pp. 97-105
    2. Goncharenko E.A., Paznikov A.A. Analysis of the efficiency of atomic operations in multi-core shared-memory computer systems // Tomsk State University Journal of Control and Computer Science, 2020. – N 51. – pp. 102–110
    3. Kholod I., Rukavitsyn A., Paznikov A., Gorlatch S. Parallelization of the self-organized maps algorithm for federated learning on distributed sources // The Journal of Supercomputing. – 2020. – P. 1-17.
    4. Paznikov A., Shichkina Y. Algorithms for Optimization of Processor and Memory Affinity for Remote Core Locking Synchronization in Multithreaded Applications // Information, 2018. – Vol. 9 – N. 1 – pp. 1-12. DOI:10.3390/info9010021
    5. Anenkov A., Paznikov A. Algorithms of optimization of scalable thread-safe pool based on diffracting trees for multicore computing systems // Tomsk state university journal of control and computer science, 2017. – N. 39 – pp. 73-84.

    Results of intellectual activity

    1. Certificate 2020663876 Russian Federation. Certificate of state registration of the computer program. Software tool implementing one-to-all communication in remote memory access model based on binomial tree / Paznikov A.A. Applicant and patent owner Saint Petersburg Electrotechnical University “LETI” (ETU “LETI”). Application 26.10.2020, published 03.11.2020.
    2. Certificate 2020663593 Russian Federation. Certificate of state registration of the computer program. Program for optimizing for large numbers calculations based on pretrained neural network / Mohammed O.T., Heidari S.M., Paznikov A.A. Applicant and patent owner Saint Petersburg Electrotechnical University “LETI” (ETU “LETI”). Application 26.10.2020, published 29.10.2020.
    3. Certificate 2019667574 Russian Federation. Certificate of state registration of the computer program. Distributed relaxed queue in remote memory access model / Paznikov A.A. Applicant and patent owner Saint Petersburg Electrotechnical University “LETI” (ETU “LETI”). Application 09.12.2019, published 25.12.2019.
    4. Certificate 2019660469 Russian Federation. Certificate of state registration of the computer program. Software for analyzing efficiency of atomic operations on multicore shared-memory systems / Paznikov A.A., Goncharenko E.A. Applicant and patent owner Saint Petersburg Electrotechnical University “LETI” (ETU “LETI”). Application 23.06.2019, published 06.08.2019.
    5. Certificate 2019618043 Russian Federation. Certificate of state registration of the computer program. Optimized concurrent relaxed priority queue / Tabakov A.V., Paznikov A.A. Applicant and patent owner Saint Petersburg Electrotechnical University “LETI” (ETU “LETI”). Application 11.06.2019, published 26.06.2019.
    6. Certificate 2018618685 Russian Federation. Certificate of state registration of the computer program. Program for optimization of critical section execution of dedicated processor cores / Paznikov A.A. Applicant and patent owner Saint Petersburg Electrotechnical University “LETI” (ETU “LETI”). Application 05.06.2018, published 17.07.2018.
    7. Certificate 2018618684 Russian Federation. Certificate of state registration of the computer program. Program of adaptive barrier synchronization algorithm in MPI standard based on LogP model / Zharikov V.V., Paznikov A.A. Applicant and patent owner Saint Petersburg Electrotechnical University “LETI” (ETU “LETI”). Application 05.06.2018, published 17.07.2018.
    8. Certificate 2015613575 Russian Federation. Certificate of state registration of the computer program. Program of reduction of distributed arrays in parallel PGAS-programs / Paznikov A., Kurnosov M. Applicant and patent owner Siberian State University of Telecommunications and Information Sciences. Application 03.02.2015, published 19.03.2015.